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technical note lcd segment driver series for 128 140 segment type lcd lcd segment driver bu9728akv, bu9795akv/fv/guw outline this is lcd segment driver for 126 to 140 segment ty pe display. there is a lineup which is suitable for multi function display and is integrated display ram and power supply circuit for lcd driving with 4 common output type: bu9728akv and bu9795akv/fv/guw. 128segment (seg32co m4) driver bu9728akv ??????? p. 1 140segment (seg35com4) driver bu9795akv/fv/guw ??????? p.10 bu9728akv 128segment (seg32com4) driver feature (bu9728akv) 1) 4wire serial interface (sck, sd, c _____ / ____ d _____ , cs __________ ) 2) integrated ram for display data (ddram) : 32 4bit (max 128 segment) 3) lcd driving port: 4 common output, 32 segment output 4) display duty: 1/4 duty 5) integrated oscillator circui t (external resister type) 6) integrated power supply circui t for lcd driving (1/3 bias) 7) low voltage / low power consumption des ign: +2.5 5.5v uses (bu9728akv) dvc, car audio, telephone absolute maximum ratings (ta=25degree, vss=0v) (bu9728akv) parameter symbol limits unit remarks power supply voltage1 vdd -0.3 +7.0 v power supply power supply voltage2 vlcd -0.3 +7.0 v lcd drive voltage allowable loss pd 400 mw when use more than ta=25 ? c, subtract 4mw per degree. operational temperature range topr -40 +85 degree storage temperature range tstg -55 +125 degree input voltage range vin -0.3 to vdd+0.3 v output voltage range vout -0.3 to vdd+0.3 v *this product is not des igned against radioactive ray. recommend operating conditions (t a=25degree, vss=0v) (bu9728akv) parameter symbol min typ max unit remarks power supply voltage1 vdd 2.5 - 5.5 v power supply voltage2 vlcd 0 - vdd v vdd R v1 R v2 R v3 R vss oscillator frequency fosc - 36 - khz rf=470k ? jul. 2008 ? this document is not de livery specifications.
2/23 electrical characteristics (bu9728akv) dc characteristics (vdd=2.5 5.5v, vss=0v, ta=25degree, unless otherwise specified) parameter symbo l limit uni t condition terminal min. typ. max. ?h? level input voltage vih1 0.8vdd - vdd v vo=0.9vdd or 0.1vdd sc1, sd, sck, c _____ / ____ d _____ , c s __________ , reset _______________________ ?l? level input voltage vil1 0 - 0.2vdd v vo=0.1vdd or 0.9vdd lcd driver on resistance ron - - 30 k ? | von|=0.1v seg0 31, com0 3 ?l? level input current1 iil1 - - 100 a vin=0 reset _______________________ ?l? level input current2 iil2 - - 2 a vin=0 osc1, sd, sck, c _____ / ____ d _____ , c s __________ ?h? level input current iih -2 - - a vin=vdd osc1, sd, sck, c _____ / ____ d _____ , c s __________ , reset _______________________ input capacitance ci - 5 - pf sd, sck, c _____ / ____ d _____ , c s __________ power consumption idd - 0.05 1 a *2 display off vdd - 40 80 a *3 display on - 100 250 a *4 mpu access *1: lcd driver on resistance is not included internal power supply impedance *2: v3=0v, all input terminal are connected to vdd or vss. *3: v3=0v, rf=470k ? , except of osc1 terminals are connected to vdd or vss. *4: v3=0v, rf=470k ? , fsck=200khz ac characteristics (vdd=2.5 5.5v, vss=0v, ta=25degree, unless otherwise specified) parameter symbo l limit unit condition min. typ. max. sck rise time ttlh - - 100 ns sck fall time tthl - - 100 ns sck cycle time tcyc 800 - - ns wait time for command twait 800 - - ns sck pulse width ?h? twh1 300 - - ns sck pulse width ?l? twl1 300 - - ns sd setup time tsu1 100 - - ns sd hold time th1 100 - - ns cs pulse width ?h? twh2 300 - - ns cs pulse width ?l? twl2 6400 - - ns cs setup time tsu2 100 - - ns cs hold time th2 100 - - ns c/d setup time tsu3 100 - - ns c/d hold time th3 100 - - ns based on sck 8 th clock rising c/d ? cs time *5 tcch 100 - - ns based on c s __________ rising c/d ? sck time *5 tsch 100 - - ns based o sck 8 th clock falling *5: should satisfy either one condition
3/23 twl1 tsu2 tcyc twh1 ttlh tthl tsu1 th1 tsch tsu3 tth3 tcch tth2 twh2 twl2 cs sck sd c/d d7 d6 d0 d7 tcyc twait sd sck fig. bu9728akv-1 interface timing fig. bu9728akv-2 command cycle reference data (bu9728akv) v dd =5v v dd =3v 100k 200k 300k 400k 500k 700k 1m 1k 700 500 400 300 200 100 70 50 40 30 20 10 oscillation registance rf( ) frame frequency fr(hz) frame freq. rf 1.0 2.0 3.0 4.0 5.0 6.0 7.0 80 70 60 50 40 30 20 10 0 supply voltage v dd (v) operating current i dd (ua) i dd v dd display accessing (v lcd =v c =v dd ,rf=470k ) fig. bu9728akv-3 frame frequency vs. resister value fig. bu9728akv-4 power consumption vs. power supply
4/23 block diagram (bu9728akv) pin arrangement (bu9728akv) fig. bu9728akv-5 block diagram fig. bu9728akv-6 pin arrangement terminal description (bu9728akv) terminal no. type function osc1 osc2 1 2 i o int clock use mode, connect re sister between osc1 and osc2. ext clock use mode, input clock from osc1, osc2 keep open. v1 v3 3 5 power supply for lcd driving. keep vdd R v1 R v2 R v3 R vss condition. vss 6 vss terminal vdd 7 vdd terminal sck 8 i serial clock input sd 9 i serial data input cs _________ 10 i chip select input ?l?: active c _____ / ____ d _____ 11 i command data judgment input ?l?: display data, ?h?: command com0 3 12 15 o lcd common output reset 16 i reset input terminal. it will be initialized with "l" level input. reset address counter, set display off status. seg0 31 17 48 o lcd segment output serial interface sd sck c/d cs command/data register command decoder address counter tim ing generator common counter display data ram (dd ram) lcd segment driver 32bits seg 0 seg 1 seg 31 lcd common driver 4bits com 1 com 2 com 0 com 3 osc 1 osc 2 lcd driver bias circuit v ss v 1 v dd v 2 v 3 rese t 123456789101112 13 14 15 16 24 23 22 21 20 19 18 17 osc 1 osc 2 v ss v dd sck sd com 1 com 2 com 3 seg 7 seg 1 seg 2 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 2 0 seg 21 seg 22 seg 2 3 seg 2 4 seg 2 5 seg 2 6 seg 2 7 v 1 v 2 v 3 cs c/d com 0 seg 3 seg 4 seg 5 seg 6 reset seg 0 36 35 34 33 32 31 30 29 28 27 26 25 seg 16 seg 17 seg 18 seg 19 seg 2 8 seg 2 9 seg 3 0 seg 31 47 46 45 44 48 37 38 39 40 41 42 43
5/23 block description (bu9728akv) ? address counter an address counter shows the address of ddram. address data are transferred to the address counter automatically when an address set is written in the command/data register. after data are written in ddram, +1 or +2 is done automatically with an address counter. the choice of +1 or +2 is done autom atically by the next condition. ddram 8bit writing (in the 8 cl ock of sck, c/d= "l") +2 ddram 4bit rewriting (in the 8 clock of sck, c/d= "h") +1 and, when it is counted to 1fh, an address becomes 00h with an address counter by the next count up. ? display data ram (ddram) a display data ram (ddram) is used to store displa y data. that capacity is 32 address 4 bits. ddram and the relations of the disp lay position are as the following. ddram address 00 01 02 03 04 05 06 07 ??????? 1d 1e 1f bit d0 com0 d1 com1 d2 com2 d3 com3 ? timing generater it will be started to oscillate by connecting rf between osc1, osc2, and generated display timing signal. also it will be able to do by external clock input. fig. bu9728akv-7 rf oscillator circuit fig. bu9728akv-8 external clock input ? lcd drive power supply lcd drive power supply occurs by bu9728akv. lcd voltage is given by vdd- v3, and it causes v1=2 ? vlcd/3, v2=vlcd/3. when input lcd power s upply by using external breeder register etc. please keep below condition. vdd R v1 R v2 R v3 R vss fig. bu9728akv-9 internal power supply use fig. bu9728akv-10 external power supply use v dd v 1 v ss v 2 v 3 v dd v 1 v ss v 2 v 3 osc 1 osc 2 rf (it is possible that oscillating frequency is changed with rf. ) osc 1 osc 2 external clock input open
6/23 detail of commands (bu9728akv) there is the following thing in the command (the 8n clock of sck is c/d= "h".) of bu9728akv. ? address set msb lsb 0 0 0 a a a a a address data shown as aaaaa by the binary system is set on the address counter. address does +2 every time indication data input (for 8bit) completes input. ? display on msb lsb 0 0 1 * * * * * *:don't care there are no relations with the cont ents of the display data ram (ddram). and all display is turned on. in this case, the contents of ddram don't change. ? display off msb lsb 0 1 0 * * * * * *:don't care there are no relations with the cont ents of the display data ram (ddram). in this case, the contents of ddram don't change. ? display start msb lsb 0 1 1 * * * * * *:don't care it will be started to oscillate and to displa y in accordance with the contents of ddram. ? rewriting of the display data ram (ddram) msb lsb 1 0 0 * d d d d *:don't care the binary four bits data dddd are written in ddram. a writing address is address ordered by the address set command. then, after this command is carried out, an address does + 1 automatically. ? reset msb lsb 1 1 0 * * * * * *:don't care please execute this command first after power on. it will be init ialized as follow conditions; ? display off ? address counter reset
7/23 recommendation circuit example (bu9728akv) fig. bu9728akv-11 when a contrast adjustment mechanism is used. input output circuit (bu9728akv) name i/o circuit name i/o circuit sd sck c _____ / ____ d _____ cs __________ i seg0 seg31 com0 com3 o name i/o circuit osc1 osc2 name i/o circuit reset _______________________ i fig. bu9728akv-14 input output circuit vdd gnd in ou t vlcd gnd vlcd gnd vdd gnd osc1 vdd gnd osc2 vd d gnd in vd d 5.0v 1m ? vss v3 v2 v1 vdd 1m ? 1m ? the value (1m ? ) of the built-in resistance value inside the figure is reference value. value varies according to terms of manufacture and so on. it can use as a resistance for the contrast adjustment when variable resistance is given to the v3-vss space. the resistance of the outside and resistance with built-in bu9728akv become the right figures in this case. the value of rc is to decide the value which met a system referring to the circuit of the right figure. rc gnd
8/23 cautions on use (1) absolute maximum ratings an excess in the absolute maximum ratings , such as supply voltage, temperature range of operating conditions , etc., can break d own devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. if any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) operating conditions these conditions represent a range within which characteristics can be provided approximately as expected. the electrical chara cteristics are guaranteed under the conditions of each parameter. (3) reverse connection of power supply connector the reverse connection of power supply connector can break down ics. take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the ic?s power supply terminal. (4) power supply line design pcb pattern to provide low impedance for the wiring betwee n the power supply and the gnd line s. in this regard, or the d igital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. for the gnd line, give consideration to design the patterns in a similar manner. furthermore, for all power supply terminals to ics, mount a capacitor between the powe r supply and the gnd terminal. at the sam e time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem inclu ding the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) gnd voltage make setting of the potential of the gnd ter minal so that it will be maintained at the minimum in any operating state. furtherm ore, check to be sure no terminals are at a potential lower than the gnd voltage including an actual electric transient. (6) short circuit between terminals and erroneous mounting in order to mount ics on a set pcb, pay thorough attention to the direction and offset of the ics. erroneous mounting can break down the ics. furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the gnd terminal, the ics can break down. (7) operation in strong electromagnetic field be noted that using ics in the strong electromagnetic field can malfunction them. (8) inspection with set pcb on the inspection with the set pcb, if a capacitor is connected to a low-impedance ic terminal, the ic can suffer stress. there fore, be sure to discharge from the set pcb by each process. furthermore, in order to mount or dismount the set pcb to/from the jig for the inspection pro cess, be sure to turn off the power supply and then mount the set pcb to the jig. after the completion of the inspection, be sure to turn off the power s upply and then dismount it from the jig. in addition, for protection against static electricity, establish a ground for the assembly process and pay th orough attention to the transportation and the storage of the set pcb. (9) input terminals in terms of the construction of ic, parasitic elements are inevitably formed in relati on to potential. the operation of the par asitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. therefore, pay thorough attention not to handle the input terminals, such as to apply to the input termin als a voltage lower than the gnd respectively, so that a ny parasitic element will operate. furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the ic. in addit ion, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) ground wiring pattern if small-signal gnd and large-current gnd are pr ovided, it will be recommended to sepa rate the large-current gnd pattern from t he small-signal gnd pattern and establish a single ground at the reference point of the se t pcb so that resistance to the wiring pattern and vo ltage fluctuations due to a large current will cause no fluctuations in voltages of the sma ll-signal gnd. pay attention not to cause fluctuations in the gnd wiring pattern of external parts as well. (11) external capacitor in order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to dc bias and changes in the capacitance due to temperature, etc. (12) no connecting input terminals in terms of extremely high impedance of cmos gate, to open the input terminals causes unstable st ate. and unstable state brings the inside gate voltage of p-channel or n-channel transistor into active. as a result, battery current may increase. and unstable state ca n also causes unexpected operation of ic. so unless otherwis e specified, input terminals not being us ed should be connected to the power supp ly or gnd line. (13) rush current when power is first supplied to the cmos ic, it is possible that the internal logic may be unstable and rush current may flow instantaneously. therefore, give special condition to power coupling capacitance, powe r wiring, width of gnd wiring, and routin g of connections.
9/23 order form name selection b u rohm form name 9 7 2 8 part no. k package type e 2 packaging and forming specification e2 =reel-shaped emboss taping a v kv=vqfp (unit:mm) 0.5 0.15 1.0 0.2 9.0 0.2 7.0 0.1 9.0 0.2 7.0 0.1 48 37 1 12 13 24 25 36 0.5 0.1 1.6max. 0.1 0.05 0.75 0.75 1.4 0.05 0.08 s 0.08 m 0.145 + 0.05 ? 0.03 0.22 + 0.05 ? 0.04 4 + 6 ? 4 vqfp48c < packin g information > *when you order , please order in times the amount of package quantity. ta p e quantit y direction of feed embossed carrier tape 1500pcs (the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) e2 reel 1pin direction of f eed
10/23 bu9795akv/fv/guw max140segment (seg35com4) driver feature (bu9795akv/afv/aguw) 1) 3wire serial interface (csb, sd, scl) 2) integrated ram for display data (ddram) : 35 4bit (max 140 segment) 3) lcd driving port: 4 common output, segment: 35output (bu9795akv), 31output (b u9795aguw), 27output (bu9795afv) 4) display duty: 1/4 duty 5) integrated buffer amp for lcd driving power supply 6) 1/2bias, 1/3bias selectable 7) no external components 8) low power/ ultra low power consumption design: +2.5 5.5v uses (bu9795akv/afv/aguw) telephone, fax, portable equipment (pos, ecr, pda etc.), dsc, dvc, car audio, home electr ical appliance, meter equipment etc. line-up parameter bu9795akv bu9795afv bu9795aguw segment output 35 27 31 common output 4 4 4 package vqfp48c ssop-b40 vbga48w040 absolute maximum ratings (ta=25degr ee, vss=0v) (bu9795akv/afv/aguw) parameter symbol limits unit remark power supply voltage1 vdd -0.5 +7.0 v power supply power supply voltage2 vlcd -0.5 vdd v lcd drive voltage allowable loss pd 0.6 w when use more than ta=25 ? c, subtract 6mw per degree.(bu9795akv) 0.7 w when use more than ta=25 ? c, subtract 7mw per degree (bu9795afv) 0.27 w when use more than ta=25 ? c, subtract 2.7mw per degree (bu9795aguw) input voltage range vin -0.5 vdd+0.5 v operational temperature range topr -40 +85 degree storage temperature range ts t g -55 +125 degree *this product is not designed against radioactive ray. recommend operating conditions (ta=25de gree,vss=0v) (bu9795akv/afv/aguw) parameter symbol min. typ. max. unit remark power supply voltage1 vdd 2.5 - 5.5 v power supply power supply voltage2 vlcd 0 - vdd-2.4 v lcd drive voltage * please use vdd-vlcd R 2.4v condition.
11/23 electrical characteri stics(bu9795akv/afv/aguw) dc characteristics (vdd=2.5 5.5v, vss=0v, ta=-40 85degree, unless otherwise specified) parameter symb ol limit unit condition min typ max ?h? level in p ut volta g e vih 0.7vdd - vdd v ?l? level in p ut volta g e vil vss - 0.3vdd v ?h? level in p ut current iih - - 1 ua ?l? level in p ut current iil -1 - - ua lcd driver on resistance seg ron - 3.5 - k ? iload=10ua com ron - 3.5 - k ? vlcd suppl y volta g e vlcd 0 - vdd -2.4 v vdd-vlcd R 2.5v standb y current ist - - 5 ua display off, oscillator off power consumption 1 idd1 - 12.5 30 ua vdd=3.3[v], ta=25, power save mode1, fr=70hz 1/3 bias, frame inverse power consumption 2 idd2 - 20 40 ua vdd=3.3[v], ta=25, normal mode, fr=80hz 1/3 bias, line inverse oscillation characterist ics (bu9795akv/afv/aguw) (vdd=2.5 5.5v,vss=0v, ta=-40 85degree) parameter symb ol limit unit condition min typ max frame frequency f clk 56 80 104 hz fr = 80hz setting frame frequency1 f clk1 70 80 90 hz vdd=3.5v, 25degree mpu interface characteri stics (bu9795akv/afv/aguw) (vdd=2.5v 5.5v,vss=0v, ta=-40 85degree) parameter symb ol limit unit condition min typ max in p ut rise time t r - - 80 ns in p ut fall time t f - - 80 ns sc l c y cle time tscy 400 - - ns ?h? sc l pulse width tshw 100 - - ns ?l? scl pulse width tslw 100 - - ns sd setup time tsds 20 - - ns sd hold time tsdh 50 - - ns csb setup time tcss 50 - - ns csb hold time tcsh 50 - - ns ?h? csb pulse width tchw 50 - - ns fig.bu9795akv/fv/guw-1 3wire serial timing waveform tchw csb scl sd tcsh tscyc tslw tshw tsds tsdh tf t r tcss
12/23 * bu9795akv block diagram pin arrangement fig. bu9795akv /afv /aguw-2a fig. bu9795akv /afv /aguw-3a bu9795akv block diagram bu9795akv pin arrangement terminal description terminal terminal no. i/o function inhb 48 i input terminal for turn off display h: turn on display l: turn off display test 47 i test input (rohm use only) must be connect to vss oscio 43 i external clock input ex clock and int clock can be changed by command. must be connect to vss when use internal oscillation circuit. sd 46 i serial data input scl 45 i serial data transfer clock csb 44 i chip select : ?l? active vss 42 gnd vdd 41 power supply vlcd 40 power supply for lcd driving seg0-34 1-35 o segment output for lcd driving com0-3 36-39 o common output for lcd driving com0 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 com1 seg23 com2 seg22 com3 seg21 vlcd seg20 vdd seg19 vss seg18 oscio seg17 csb seg16 scl seg15 sd seg14 test seg13 inhb seg12 37 48 24 13 36 25 1 2 1 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 1 2 1 lcd bias selector common driver segment driver oscillator power on reset s d sc l vlcd oscin vs s com0 com3 seg0 seg34 if filter serial inter face command register common counter ddram lcd voltage generato r command data decoder blink timing generator vd d csb test inhb
13/23 * bu9795afv block diagram pin arrangement fig. bu9795akv /afv /aguw-2b fig. bu9795akv /afv /aguw-3b bu9795afv block diagram bu9795afv pin arrangement terminal description terminal terminal no. i/o function inhb 36 i input terminal for turn off display h: turn on display l: turn off display test 35 i test input (rohm use only) must be connect to vss oscio 31 i external clock input ex clock and int clock can be changed by command. must be connect to vss when use internal oscillation circuit. sd 34 i serial data input scl 33 i serial data transfer clock csb 32 i chip select : ?l? active vss 30 gnd vdd 29 power supply vlcd 28 i power supply for lcd driving seg4-30 1-23, 37-40 o segment output for lcd driving com0-3 24-27 o common output for lcd driving lcd bias selector common driver segment driver oscillator power on reset sd scl vlcd oscin vss com0 com3 seg4 seg30 if filter serial inter face command register common counter ddram lcd voltage generato r command data decoder blink timing generator vdd csb test inhb seg22 seg21 seg17 seg20 seg16 seg23 seg19 seg10 seg8 seg9 seg11 seg12 seg13 seg14 seg15 seg18 seg26 seg25 seg24 seg27 scl sd seg5 test seg6 csb inhb seg30 seg28 seg29 com0 com2 com3 seg7 seg4 vdd vss oscio vlcd com1 1 20 21 40
14/23 * bu9795aguw block diagram pin arrangement fig. bu9795akv /afv /aguw-2c fig. bu9795akv /afv /aguw-3c bu9795aguw block diagram bu9795aguw pin arrangement terminal description terminal i/o function inhb i input terminal for turn off display h: turn on display l: turn off display test i test input (rohm use only) must be connect to vss oscio i external clock input ex clock and int clock can be changed by command. must be connect to vss when use internal oscillation circuit. sd i serial data input scl i serial data transfer clock csb i chip select : ?l? active vss gnd vdd power supply vlcd i power supply for lcd driving seg2-32 o segment output for lcd driving com0-3 o common output for lcd driving (caution) about terminal number, please refer to above pin arrangement lcd bias selector common driver segment driver oscillator power on reset sd scl vlcd oscin vss com0 com3 seg2 seg32 if filter serial inter face command register common counter ddram lcd voltage generato r command data decoder blink timing generator vdd csb test inhb 1234567 g (nc) seg13 seg15 seg18 seg20 seg22 (nc) f seg11 seg12 seg16 seg17 seg21 seg23 seg24 e seg9 seg10 seg14 seg19 seg25 seg27 seg26 d seg7 seg6 seg8 seg5 seg30 seg28 seg29 c seg4 seg3 seg2 csb com3 seg32 seg31 b inhb sd vss vdd com1 com0 a (nc) test2 scl oscio vlcd com2 (nc)
15/23 command description (bu9795akv/afv/aguw) d7 (msb) is bit for command or data judgment. refer to command and data transfer method. c: 0: next byte is ram write data. 1: next byte is command. mode set (mode set) msb d7 d6 d5 d4 d3 d2 d1 lsb d0 c 1 0 * p3 p2 * * (*:don?t care) set display on and off setting p3 reset initialize condition display off (dispoff) 0 display on (dispon) 1 set bias level setting p2 reset initialize condition 1/3 bias 0 1/2 bias 1 address set (adset) msb d7 d6 d5 d4 d3 d2 d1 lsb d0 c 0 0 p4 p3 p2 p1 p0 address data is specified in p[4:0] and p2 (icset command) as follows. msb lsb internal register address [5] address [4] ??? address [0] bit of each command icset [p2] adset [p4] ??? adset [p0]
16/23 display control (disctl) msb d7 d6 d5 d4 d3 d2 d1 lsb d0 c 0 1 p4 p3 p2 p1 p0 set frame frequency settin g p4 p3 reset initialize condition 80hz 0 0 71hz 0 1 64hz 1 0 53hz 1 1 set lcd drive waveform settin g p2 reset initialize condition line inversion 0 frame inversion 1 set power save mode settin g p1 p0 reset initialize condition power save mode 1 0 0 power save mode 2 0 1 normal mode 1 0 high power mode 1 1 vdd-vlcd>=3.0v is required for high power mode. set ic operation (icset) msb d7 d6 d5 d4 d3 d2 d1 lsb d0 c 1 1 0 1 p2 p1 p0 p2: msb data of ddram address. please refer to ?adset? command. setting p2 reset initialize condition address msb?0? 0 address msb?1? 1 set software reset condition setting p1 no operation 0 software reset 1 switch between internal clock and external clock. setting p0 reset initialize condition internal clock 0 external clock input 1
17/23 blink control (blkctl) msb d7 d6 d5 d4 d3 d2 d1 lsb d0 c 1 1 1 0 * p1 p0 set blink condition setting p1 p0 reset initialize condition off 0 0 0.5 hz 0 1 1 hz 1 0 2 hz 1 1 all pixel control (apctl) msb d7 d6 d5 d4 d3 d2 d1 lsb d0 c 1 1 1 1 1 p1 p0 all display set on. off setting p1 reset initialize condition normal 0 all pixel on 1 setting p0 reset initialize condition normal 0 all pixel off 1 .
18/23 0000000 a b c d e f g h i j k l m n o p ? display data command function description (bu9795akv/afv/aguw) command and data transfer method 3-spi (3wire serial interface) this device is controlled by 3-wire signal (csb, scl, and sd). first, interface counter is initialized with csb=?h", and csb=?l? makes sd and scl input enable. the protocol of 3-spi transfer is as follows. each command starts with command or data judgment bit (d/c) as msb data, and continuously in order of d6 to d0 are followed after csb =?l?. (internal data is latched at the rising edge of scl, it converted to 8bits parallel data at the falling edge of 8 th clk.) d/c = ?h? : command d/c = ?l? : data fig. bu9795akv /afv /aguw-10 3-spi command/data transfer format write display data and transfer method * bu9795akv this lsi have display data ram (ddram) of 354=140bit. the relationship between data input and display data, ddram data and address are as follows. 8 bit data will be stored in ddram. the address to be written is the address specified by address set command, and t he address is automatically incremented in every 4bit data. data can be continuously written in ddram by transmitting data continuously. (when ram data is written successively after writing ram data to 22h (seg34), the address is returned to 00h (seg0) by the auto-increment function. ddram address 00h 01h 02h 03h 04h 05h 06h 07h ???????? 1eh 1fh 20h 21h 22h bit 0 a e i m q u com0 1 b f j n r v com1 2 c g k o s x com2 3 d h l p t y com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 ???????? seg30 seg31 seg32 seg33 seg34 as data transfer to ddram happens every 4bit data, it will be cancelled if it changes csb=?l? ?h? before 4bits data transfer. command command/data d5 scl csb sd d2 d1 d0 d7 d/cd6d5d4d3d2d1d0 d/c d1d0d7 d6 d6 d5 d4 d3 d6 d5 d4 d3 d2
19/23 * bu9795afv as seg0, seg1, seg2, seg3, seg31, seg32, seg33, seg34 are not output, these address will be dummy address. ddram address 00h 01h 02h 03h 04h 05h 06h 07h ???????? 1eh 1fh 20h 21h 22h bit 0 a e i m q u com0 1 b f j n r v com1 2 c g k o s x com2 3 d h l p t y com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 ???????? seg30 seg31 seg32 seg33 seg34 as data transfer to ddram happens every 4bit data, it will be cancelled if it changes csb=?l? ?h? before 4bits data transfer. * bu9795aguw as seg0, seg1, seg33, seg34 are not outpu t, these address will be dummy address. ddram address 00h 01h 02h 03h 04h 05h 06h 07h ???????? 1eh 1fh 20h 21h 22h bit 0 a e i m q u com0 1 b f j n r v com1 2 c g k o s x com2 3 d h l p t y com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 ???????? seg30 seg31 seg32 seg33 seg34 as data transfer to ddram happens every 4bit data, it will be cancelled if it changes csb=?l? ?h? before 4bits data transfer. reset (initial) condition initial condition after execute software reset is as follows. ? display is off. ? ddram address is initialized (ddram data is not initialized). ? refer to command description about initialize value of register. dummy data dummy data dummy data dummy data
20/23 cautions of power-on condition (bu9795akv /afv /aguw) this lsi has ?p.o.r? (power-on reset) circuit and software reset function. please keep the following recommended power-on conditions in order to power up properly. 1. please set power up conditions to meet the recommended tr, tf, toff, and vbot spec below in order to ensure p.o.r operation. recommendation condition of tr,tf,toff,vbot tr tf toff vbot less than 1ms less than 1ms more than 150ms less than 0.1v vdd tf tr toff vbot power on/off fig. bu9795akv /afv /aguw-18 power on-off waveform 2. if it is difficult to meet above conditions, execute the following sequence after power-on. because it doesn?t accept the command in power off, it is necessary to care that correspondence by software reset doesn?t become alternative to por function completely. (1) csb=?l? ?h? condition fig. bu9795akv-19 csb timing (2) after csb?h? ?l?, execute software reset (icset command). io circuit (bu9795akv /afv /aguw) fig. bu9795akv /afv /aguw-20 io circuit v dd csb vdd vlcd vss vdd inhb vss vdd test vss vdd oscin vss vdd vss vdd csb, sd, scl vss
21/23 cautions on use (1) absolute maximum ratings an excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break d own devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. if any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) operating conditions these conditions represent a range within which characteristics can be provided approximately as expected. the electrical chara cteristics are guaranteed under the conditions of each parameter. (3) reverse connection of power supply connector the reverse connection of power supply connector can break down ics. take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the ic?s power supply terminal. (4) power supply line design pcb pattern to provide low impedance for the wiring between the power supply and the gnd lines. in this regard, or the d igital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. for the gnd line, give consideration to design the patterns in a similar manner. furthermore, for all power supply terminals to ics, mount a capacitor between the power supply and the gnd terminal. at the sam e time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem inclu ding the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) gnd voltage make setting of the potential of the gnd terminal so that it will be maintained at the minimum in any operating state. furtherm ore, check to be sure no terminals are at a potential lower than the gnd voltage including an actual electric transient. (6) short circuit between terminals and erroneous mounting in order to mount ics on a set pcb, pay thorough attention to the direction and offset of the ics. erroneous mounting can break down the ics. furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the gnd terminal, the ics can break down. (7) operation in strong electromagnetic field be noted that using ics in the strong electromagnetic field can malfunction them. (8) inspection with set pcb on the inspection with the set pcb, if a capacitor is connected to a low-impedance ic terminal, the ic can suffer stress. there fore, be sure to discharge from the set pcb by each process. furthermore, in order to mount or dismount the set pcb to/from the jig for the inspection pro cess, be sure to turn off the power supply and then mount the set pcb to the jig. after the completion of the inspection, be sure to turn off the power s upply and then dismount it from the jig. in addition, for protection against static electricity, establish a ground for the assembly process and pay th orough attention to the transportation and the storage of the set pcb. (9) input terminals in terms of the construction of ic, parasitic elements are inevitably formed in relation to potential. the operation of the par asitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the gnd respectively, so that a ny parasitic element will operate. furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the ic. in addit ion, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) ground wiring pattern if small-signal gnd and large-current gnd are provided, it will be recommended to separate the large-current gnd pattern from t he small-signal gnd pattern and establish a single ground at the reference point of the set pcb so that resistance to the wiring pattern and vo ltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal gnd. pay attention not to cause fluctuations in the gnd wiring pattern of external parts as well. (11) external capacitor in order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to dc bias and changes in the capacitance due to temperature, etc. (12) no connecting input terminals in terms of extremely high impedance of cmos gate, to open the input terminals causes unstable state. and unstable state brings the inside gate voltage of p-channel or n-channel transistor into active. as a result, battery current may increase. and unstable state ca n also causes unexpected operation of ic. so unless otherwise specified, input terminals not being used should be connected to the power supp ly or gnd line. (13) rush current when power is first supplied to the cmos ic, it is possible that the internal logic may be unstable and rush current may flow instantaneously. therefore, give special condition to power coupling capacitance, power wiring, width of gnd wiring, and routin g of connections.
22/23 order form name selection ( unit:mm ) ssop-b40 0.22 0.1 0.65 0.15 0.1 0.3min. 7.8 0.3 5.4 0.2 1.8 0.1 0.1 1 40 20 21 13.6 0.2 0.1 0.08 m ta p e quantit y direction of feed embossed carrier ta p e 2000 p cs e2 (the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) reel 1pin 1234 1234 1234 1234 1234 1234 1234 1234 when you order , please order in times the amount of package quantity. direction of feed b u rohm form name 9 7 9 5 part no. k package type e 2 packaging and forming specification e2 =reel-shaped emboss taping a v (unit:mm) 0.5 0.15 1.0 0.2 9.0 0.2 7.0 0.1 9.0 0.2 7.0 0.1 48 37 1 12 13 24 25 36 0.5 0.1 1.6max. 0.1 0.05 0.75 0.75 1.4 0.05 0.08 s 0.08 m 0.145 + 0.05 ? 0.03 0.22 + 0.05 ? 0.04 4 + 6 ? 4 vqfp48c < packin g information > *when you order , please order in times the amount of package quantity. ta p e quantit y direction of feed embossed carrier tape 1500pcs (the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) e2 reel 1pin direction of feed kv=vqfp fv= ssop-b guw=vbga tape quantity direction of feed embossed carrier tape (with dry pack) 2500pcs e2 (the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand.) reel 1pin 1234 1234 1234 1234 1234 1234 ( unit:mm ) v bga048w040 direction of feed when you order , please order in times the amount of package quantity. a b s sab m 0.05 4 8- 0.295 0.05 1pin mark e 0.5 4 0.9max g 4.0 0.1 4.0 0.1 f 3 s 0.08 p=0.5 6 p=0.5 6 0.5 1 0.10 2 0.5 0.1 0.5 0.1 b a 7 c 6 d 5
23/23 catalog no.08t313a '08.7 rohm ?
appendix-rev4.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / europe / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2009 rohm co.,ltd. 21 saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when de signing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no re- sponsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. rohm does not grant you, explicitly or implicitly, any license to use or exer cise intellectual property or other rights held by rohm and other parties. rohm shall bear no re- sponsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, elec- tronic ap pliances and amusement devices). the products are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possi bility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which re quires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intend- ed to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

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